1. Field of the Invention
This invention relates generally to integrated circuits and more particularly to circuit structures, methods of use, and apparatus implementing column redundancy in memory architectures.
2. Description of the Related Art
Semiconductor memory cores are typically laid-out in array format. The array structures are typically composed of 2n by 2m individual memory cells which are coupled to wordline (rows) and complementary pair bit lines (columns). A typical memory cell may be composed of transistors coupled together to form a data storage device. An individual memory cell is typically selected when an X-decoder is used to select rows and a Y-decoder is used to select columns.
In the manufacture of semiconductor memories, defects are frequently encountered. Such defects typically affect a small number of memory elements in the memory. To prevent rejection of an entire chip due to the presence of a comparatively small number of defective memory elements and to increase manufacturing process yield, typical semiconductor memory designs provide redundant memory elements arranged in well known bank architectures. Redundant memory elements are used as replacements for elements that, during testing of the memory device, are determined to be defective. Redundancy circuitry typically includes laser programmable fuses or other non-volatile memory elements suitable for storing address configurations corresponding to defective memory elements. For example, a defective row or column may be deselected and a redundant row or column assigned in its place. If done properly, the assignment of the redundant row or column is substantially transparent to a system utilizing the memory through the memory's addressing circuitry.
As mentioned above, defective rows or columns must be disabled to allow the circuit to function properly. Typically, to disable a defective row or column, redundancy circuits physically disable the defective row or column (e.g., by fusible links) or logically deselect the defective row or column (e.g., based on a defective row/column address stored in non-volatile memory). As it is common for fuse links to be located inside the memory circuitry, blowing a fuse using known laser systems becomes a slow and intricate process requiring expensive equipment.
Unfortunately, the redundant rows and columns of a redundant array that uses a bank architecture occupies valuable chip surface area and augments the unit cost of the integrated circuit. Moreover, the chip surface area occupied by the redundant array is a larger percentage of overall memory area for smaller memory configurations. In addition, the column replacement is performed by circuitry in the y-decode, i.e., at the column level, that is associated with each column in order to shift the data. The column replacement circuitry in the y-decode further occupies chip surface area.
As a result, there is a need to solve the problems of the prior art to allow for the reassignment of a defective column in real time through a simple and elegant modification of a memory integrated circuit without substantially increasing chip surface area demands or the cost of the device in light of the smaller memory configurations being produced.